Dr. Michael S. Hsiao Professor Office: 355 Durham Mailing Address: 302 Whittemore (0111) Virginia Tech Blacksburg, VA 24061 Tel: (540) 231-9254 Fax: (540) 231-3362 Email: Web page: http://www.ece.vt.edu/faculty/hsiao.html

Biography:

Michael Hsiao received the B.S. in computer engineering with highest honors from the University of Illinois at Urbana-Champaign in 1992, and M.S. and Ph.D in electrical engineering in 1993 and 1997, respectively, from the same university. During his studies, he was recipient of the Digital Equipment Corp. Fellowship and McDonnell Douglas Scholarship.
He was a visiting scientist at NEC USA in Princeton, NJ, during the summer of 1997. Between 1997 and 2001, Dr. Hsiao was an Assistant Professor in the Department of Electrical and Computer Engineering at Rutgers, the State University of New Jersey. Since 2001, he has been an Associate Professor in the Bradley Department of Electrical and Computer Engineering at Virginia Tech.

Michael is a recipient of the National Science Foundation CAREER Award.
He and his research group have published more than 130 refereed journal and conference papers, with emphasis on testing, verification, and power management of complex hardware and software systems. With the advances in software defined radios and cognitive radios, ensuring the embedded software and hardware engines function correctly is an utmost concern.
His research also encompasses testing and verification of next-generation nano-scale designs. Michael is a College of Engineering Faculty Fellow, and is a member of ACM and a senior member of IEEE.

Research Interests:

• Test and verification of hardware and software systems
• Verification of security protocols
• Power management of complex systems

Selected Publications:

• L. Zhang, I. Ghosh, and M. S. Hsiao,"A framework for automatic design validation of RTL circuits via ATPG techniques ,"
  accepted to the IEEE Transactions on Computer-Aided Design of Integrated Circuit s and Systems, 2006.
• Q. Wu and M. S. Hsiao,"State variable extraction and partitioning to reduce problem complexity for ATP G and design validation,"
  accepted by the IEEE Transactions on Computer Aided Design of Integrated Circuit s and Systems, 2006.
• X. Chen and M. S. Hsiao,"Testing embedded sequential cores in parallel using spectrum-based BIST,"
  in the IEEE Transactions on Computers, vol. 55, no. 2, pp. 150-162, February 200 6.
• L. Zhang, M. R Prasad, and M. S. Hsiao,"Interleaved invariant checking with dynamic abstraction,"
  in Proceedings of the ACM Conf. on Correct Hardware Design and Verification Meth ods, October 2005, pp. 81-96.
• K. Chandrasekar and M. S. Hsiao,"State set management for SAT-based unbounded model checking,"
  in Proceedings of the IEEE International Conference on Computer Design, October 2005, pp. 585-590.
• S. Yardi, K. Channakeshava, M. S. Hsiao, T. Martin, and D. S. Ha, "A formal framework for modeling and analysis of system-level dynamic power mana gement," in Proceedings of the IEEE International Conference on Computer Design, October 2005, pp. 119-126.
• X. Zheng and M. S. Hsiao,"Region-level approximate computation reuse for power reduction in multimedia ap plications,"
  in Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, August 2005, pp. 119-122.
• L. Zhang, M. R. Prasad, M. S. Hsiao, and T. Sidle, "Dynamic abstraction using SAT-based BMC," in the IEEE/ACM Design Automation Conference, June 2005, pp. 754-757.
• K. Chandrasekar and M. S. Hsiao,"Decision selection and learning for an 'all solutions ATPG engine'," in Proceedings of the IEEE International Test Conference, October 2004, pp. 607-616.
• P. Gupta and M. S. Hsiao,"High quality ATPG for delay defects," Proceedings of the IEEE International Test Conference, September, 2003, pp. 584- 591.