Dr. Peter Athanas Professor Office: 2040-B Torgersen Mailing Address: 302 Whittemore (0111) Virginia Tech Blacksburg, VA 24061 Tel: (540) 392-7250 Fax: (540) 231-3362 Email: Web page:http://www.ece.vt.edu/faculty/athanas.html

Biography:

Peter Athanas is a professor in the Bradley Department of Electrical and Computer Engineering at Virginia Tech.  His research interests include high-performance embedded computing, configurable computing, VLSI, and signal processing.  Athanas received his BS degree in electrical engineering from The University of Toledo, his MS degree in electrical engineering from Rensselaer Polytechnic Institute, his Sc.M. degree in applied mathematics at Brown University, and a Ph.D. degree in electrical engineering from Brown University.   His Ph.D work in 1988 focused on configurable computing architectures and compilers.  Prior to academics, Athanas also served as a senior design engineer in the Advanced Technologies Group at United Technologies Hamilton Standard in Windsor Locks, CT.  Duties included the design and supervision of several integrated circuits for avionic flight control and engine control systems.   Dr. Athanas is active in the area of configurable computing -- an emerging technology with the potential of providing the needed performance for contemporary and emerging computationally demanding signal processing applications.    He holds two patents, and  is a senior member of the IEEE Computer Society.   Dr. Athanas is currently co-director of the Virginia Tech Configurable Computing Laboratory.  The laboratory participates in a diversity of research projects related to configurable computing, sensor networks, remote sensing, and scientific computing. 

Research Interests:

• reconfigurable computing
• hardware & software security and anti-tamper
• computational aspects of software defined radios

Selected Publications :

• Anthony J. Mahar, Peter M. Athanas, Stephen D. Craven, Joshua N. Edmison, and Jonathan Graf, "Design and Characterization of a Hardware Encryption Management Unit for Secure Computing Platforms", Proceedings of the 39th Hawaii International Conference on System Sciences, HICSS 2006 / MOCHA 2006, Kauai, HI, Jan 2006.
• Jonathan Graf and Peter Athanas, "A Key Management Architecture for Securing Off-Chip Data Transfers", Proceedings of the 14th International Workshop on Field-Programmable Logic and Applications, FPL 2004, Antwerp, Belgium, Aug 2004.
• Deepak Agarwal and Peter Athanas, “An 8 GHz Ultra-Wide bad Transceiver Prototyping Testbed,” to appear at the 16th International Workshop on Rapid Systems Prototyping, Montreal, Canada, June 2005.
• Scott Harper and Peter Athanas, “A Security Policy for Hardware Encryption,” at the 37th Hawaii International Conference on Computing Systems, Waikoloa, HI,  January, 2004.
• Kiran Puttagowda, William Worek, Jae Park, and Peter Athanas, “A Run-Time Reconfigurable System for Gene Sequence Searching,” in the International Conference on VLSI Design, 8 pp., Bangalore, India, January 2003. 
• Srikathyayani  Srikanteswara, James  Neel, Jeffrey H.  Reed and Peter Athanas, "Soft radio implementations for 3G and future high data rate systems", in GLOBECOM 2001 - IEEE Global Telecommunications Conference, no. 1, pp. 3370-3374, November 2001. 
• Maneesh Soni, Kiran Puttagowda, and Peter Athanas, “VLSI Implementation of Stallion, a Wormhole Runtime Reconfigurable Processor,” at the International Conference on VLSI Design, 1 pp. (poster), Bangalore, India, July 2001.
• Peter Athanas, H. F. Silverman,  "Processor Reconfiguration Through Instruction Set Metamorphosis:  Architecture and Compiler," IEEE Computer, vol. 26, no. 3, pp. 11-18, March 1993.
• Peter Athanas, Lynn Abbott, "Processing Images in Real Time on a Custom Computing Platform," IEEE Computer, vol. 28, no. 2, pp. 16-24, February 1995.